1. Field of the Invention
The present invention relates to a control device and an information processing apparatus.
2. Description of the Related Art
An information processing apparatus such as a multi function peripheral (MFP) has been proposed, for example, in Japanese Patent Application Laid-open No. 2005-267097, that is configured by connecting a main system that serves as a main component for an image process and a sub-system that controls power and a low level network process in a power saving mode.
An example of the information processing apparatus that can be configured by connecting a main system and a sub-system with a bus is a processor adopting the configuration shown in FIG. 6. An information processing apparatus 100 shown in FIG. 6 is configured by connecting a main system 101 and a sub-system 102 with a peripheral component interconnect (PCI) bus 103.
The main system 101 includes a central processing unit (CPU) 104 that controls a process of the entire device, a memory controller hub (MCH) 105 that includes a memory controller, a main memory 106, an image processing application specific integrated circuit (image processing ASIC) 107, and an input/output (I/O) controller hub (ICH) 108 that includes an I/O controller. On the other hand, the sub-system 102 includes a system-on-a-chip (SOC) (hereinafter, “I/O-SOC”) 109 that includes a network controller and a CPU that controls the network controller. The information processing apparatus 100 includes power regulators 110 and 111 for each component. The I/O-SOC 109 controls power of the information processing apparatus 100 and a low level network process when the information processing apparatus 100 is in a power saving mode.
The transition from a normal mode to the power saving mode of the information processing apparatus 100 is explained.
When the CPU 104 instructs the I/O-SOC 109 to shift to the power saving mode, the I/O-SOC 109 enters a network response able state.
When the CPU 104 instructs the MCH 105 to shift to a self-refresh mode, the main memory 106 shifts to the self-refresh state.
When the CPU 104 instructs the I/O-SOC 109 to partially turn off the power of the main system 101, the I/O-SOC 109 receives the instruction and instructs the power regulator 110 to turn off the power of target units. The power of the CPU 104, the MCH (excluding the memory controller) 105, the image processing ASIC 107, and the ICH (excluding the interface unit with the MCH 105) 108 are turned off. As a result, the mode shifts from the normal mode to the power saving mode.
Thereafter, the I/O-SOC 109 monitors the network packets and stands by for input of an apparatus return factor packet.
Next, the return from the power saving mode to the normal mode is explained.
The I/O-SOC 109 monitors the network packets. The I/O-SOC 109 itself operates a response process for a low level self hit packet (transmission control protocol/internet protocol (TCP/IP) layer 2 and below, for example, an address resolution protocol (ARP) and an internet control message protocol (ICMP)). A filter function in the I/O-SOC 109 rejects the packets that did not hit.
On the other hand, for a high level self hit packet (TCP/IP layer 3 and above, for example, a simple network management program (SNMP)), the I/O-SOC 109 determines that the I/O-SOC 109 itself cannot process the packet (an item that needs to be processed in the CPU 104 side) and boots up the main system 101. To boot up the main system 101, the I/O-SOC 109 instructs the power regulator 110 to turn on the power of the target units, and turns on the power of the CPU 104, the MCH 105, the image processing ASIC 107, the ICH 108, and the like.
When the power of the ICH 108 is turned on, the ICH 108 first releases a reset of the MCH 105. Then, the memory controller of the MCH 105 performs a self-refresh release process, and the main memory 106 returns to the normal state.
Next, the ICH 108 releases a reset of the CPU 104, and activates the CPU 104. Then, the CPU 104 starts fetching a program code from the main memory 106, and enters a network response able state.
After that, the CPU 104 notifies the I/O-SOC 109 that the CPU 104 was able to return from the power saving mode, and the I/O-SOC 109 stops the network response process. Thereafter, the CPU 104 performs the network response.
The information processing apparatus 100 that includes the main system 101 and the sub-system 102 can attempt to save power of the main system 101 without packet loss by performing the low level response process of the network on the sub-system 102 (the I/O-SOC 109) side with less electric power and sharing the network response process between the CPU 104 and the I/O-SOC 109 by switching a network processing position in the power saving mode and the normal system mode.
However, the following problems clearly exist.
(1) Network Performance (speed)
(2) Controller Option Performance (speed)
(3) Network Process Load of CPU (large load)
(4) Complication of Network Process Unit
The problems are explained one by one.
The network performance (speed) (1) is easily affected by the performance of the parallel bus represented by the PCI bus. When the system is normal such as during network receiving, the data is transferred from a receive buffer of the I/O-SOC 109 to the main memory 106 via a direct memory access (DMA) transfer, and the CPU 104 performs a packet analysis process. When network sending, the data is transferred from the main memory 106 to a send buffer of the I/O-SOC 109 via the DMA transfer.
When the PCI bus 103 operates at 33 megahertzes and is 32 bits wide and effective efficiency thereof is 50%, the bandwidth becomes 528 megabits per second, and when the usage rate of receiving and sending is assumed to be 50%, each of the receiving and the sending is calculated to be able to use 264 megabits per second. This means that it completely becomes bus bottleneck and that the speed cannot be achieved when assuming a high speed internet represented by a gigabit Ethernet. Furthermore, the packet length actually varies, large or small, a good usage rate of the efficiency described above cannot be achieved, and a further reduction of the effective bandwidth is predicted.
For the controller option performance (speed) (2), the PCI bus is used for both the interface between the main system 101 and the sub-system 102 and the network interface of the I/O-SOC 109, so that the rate of acquiring a bus right decreases when the network process is high, i.e., when the usage rate of the PCI bus is high. Therefore, it may be difficult to exhibit a stable performance.
For the network process load of the CPU 104 (3), all packets are processed by the CPU 104 in normal system mode. However, the network process load of the CPU 104 is predicted to be high at this time because the CPU 104 reads all packets that are received in the CPU 104, and the CPU 104 determines unnecessary packets and necessary packets.
For the complication of the network process unit (4), the network process is shared between the CPU 104 and the I/O-SOC 109 by switching a network processing position in the power saving mode and the normal system mode. Therefore, a double mounting of components, an increase of procedures when switching the mode, and an increase of system cost can be predicted.